Cache memory systems have been developed to enable a data processing system to access information more quickly and more efficiently. However, with the increased efficiency, flexibility and user control of the cache memory system have been limited. Such limitations are generally considered to be necessary to prevent a user from inadvertently causing an error during operation and are well known in the engineering community.
In most data processors, two levels of privilege are provided to control access to memory, cache or otherwise, during external bus transactions and to control operation of the data processor. A supervisor mode provides the highest level of privilege. When in supervisor mode, the data processor may access memory designated for both the supervisor mode and a user mode of operation. Additionally, the supervisor mode allows execution of all instructions and access to all register locations in the data processor. Typically, operating system software is executed when the data processor is in supervisor mode. Among the operating system services provided are resource allocation of both memory and peripherals, exception handling, and software execution control. Software execution control usually includes control of a user program and protecting the system from accidental or malicious corruption by a user program.
A user mode provides a second level of privilege. When in the user mode of operation, only the memory and registers designated for use in the user mode may be accessed. Additionally, only instructions stored in a user instruction memory may be referenced. For example, in the MC88100 RISC processor available from Motorola, Inc. of Austin, Tex., four instructions are accessible only in the supervisor mode of operation. Three of these instructions execute read/write accesses to a register which may only be accessed when the data processor is in a supervisor mode of operation. A fourth instruction executes an orderly termination of an exception processing routine.
If a memory, register, or instruction specified for use only in supervisor mode, is accessed when the data processor is in user mode, an exception may occur. The exception results in an interruption of operation of the data processor. A exception handler routine is then executed to process the exception and restore the data processor to a normal mode of operation.
Additionally, the data processor may only operate in supervisor mode in certain conditions. For example, the data processor operates in supervisor mode when an exception occurs. The data processor must be in supervisor mode to execute an appropriate exception processing routine. Similarly, when a reset of the data processor occurs, the data processor operates in supervisor mode. The privilege level of the data processor may also be modified by a "trap" instruction executed in user mode. For more information about exceptions and the user and supervisor modes of operation, refer to the second edition of the MC88100 RISC Microprocessor User's Manual published by Motorola, Inc. in 1990.
Limited control of a cache memory in a data processing system is typically only allowed in the supervisor mode of operation which is not readily accessible to a user of the system. For example, in the MC88200 cache/memory management unit developed by Motorola, Inc. of Austin, Tex., a single cache control operation is executed only in the supervisor mode of operation All other cache control operations are controlled internally and are not accessible to the user even in the supervisor mode of operation. For more information regarding the MC88200 cache/memory management unit, refer to the second edition of the MC88200 Cache/Memory Management Unit User's Manual published by Motorola, Inc. in 1990.
The cache control operation which is executable in supervisor mode is a "flush" operation. In a flush operation, a modified, or "dirty," storage location in the cache memory is cleared by moving, or flushing, the dirty storage location out of the cache memory. Typically, the dirty storage location is cleared when the storage location must be allocated for a new data value.
Other cache control operations which are typically executed during cache operation, but are not accessible to the user in any mode of operation, include a "cache load" operation. During the cache load operation, data is stored in the cache memory only when a "miss" occurs because the requested data value is not stored in the cache memory. When the miss occurs, a line in the cache memory must first be allocated to receive a data value. The data is subsequently read and stored at that line. Because the data must be retrieved from an external memory source, delays occur and the efficiency of the data processing system is decreased. Additionally, unnecessary bus cycles are often executed during the allocation and filling of the line in the cache memory. As was previously stated, the user is not allowed to initiate a cache load operation in any mode of operation. The cache load operation is simply a by-product of normal cache operation which may not be affected by the user.
In each of the cache control operations listed above, the user of the data processor does not have control over cache operation except for a flush instruction operation which may be executed when the data processor is in supervisor mode. Even then, supervisor mode is not easy to access, and if accessed, may result in catastrophic errors if not correctly used. Additionally, the processing time associated with modifying the privilege level of the data processor is often prohibitively long. Each of the cache control operations described above is executed in accordance with a predetermined algorithm which is designed to maximize efficiency of the data processing system. However, exceptions do occur in which the algorithm does not provide the most efficient operation of the cache memory system. In the case of an exception, the user is not able to maintain the most efficient operation of the cache memory because the data processing system is not directly controllable Therefore, a need exists for a data processing system which allows more flexibility in executing cache control operations. Additionally, a user of the data processing system should have more insight into and an ability to maximize the efficient operation of the cache memory.